The recent disclosure by He Tingbo, Huawei’s Semiconductor Business Department president, regarding the “Tau (τ) Scaling Law” marks a pivotal inflection point in the global semiconductor landscape. As someone who closely monitors the intersection of industrial manufacturing and technological policy, I find this transition away from the traditional geometric scaling of Moore’s Law not just a tactical adjustment, but a fundamental paradigm shift. When we analyze the trajectory of electronic systems, we have long been tethered to the assumption that shrinking transistor dimensions is the sole path to efficiency. However, with physical limits approaching a critical threshold, Huawei’s transition toward “time scaling” suggests that the industry may need to pivot toward architectural innovation—specifically LogicFolding—to maintain performance gains.
The significance of this cannot be overstated. For the past seven years, Huawei has operated under intense external constraints, which effectively forced them into a “technical isolation” period. In this environment, they shifted their focus from merely integrating more components onto a single die to fundamentally optimizing signal propagation delays. By utilizing LogicFolding to essentially “fold” logic areas and leverage high-density vertical interconnects, Huawei claims to be optimizing performance density without the reliance on increasingly expensive and scientifically volatile sub-nanometer lithography processes. From a cost-efficiency perspective, this is a brilliant maneuver. If they can improve transistor density and signal processing efficiency by even 20–30% through architectural logic rather than just hardware shrinking, the return on investment for R&D becomes significantly more sustainable.
This development also highlights a broader trend in industrial strategy. Huawei’s report of developing 381 independent chips across optical communications, 5G, and AI computing architectures serves as a validation of their pivot. Their strategy mirrors the rigor found in high-precision manufacturing, where balancing the trade-off between power consumption and computational output—measured in TOPS (Tera Operations Per Second) per watt—is the primary KPI. For the average consumer and industrial client, this means that the upcoming Kirin chipsets are not just iterative upgrades; they represent a departure from the conventional scaling cycle. Huawei is essentially betting that by mastering the “time” variable—managing signal frequency and latency through architectural innovation—they can overcome the “physical wall” that has plagued the industry for the last decade.
The discussion surrounding this new theory, as detailed in reports by the People’s Daily, serves as a reminder that fundamental research is the backbone of long-term competitiveness. It is highly probable that the global semiconductor industry, which currently faces rising costs in multi-patterning and extreme ultraviolet lithography, will eventually have to reconcile with the limitations of current geometric scaling models. Whether the Tau Scaling Law becomes the new industry standard remains to be seen; however, as an engineer-led organization, Huawei is clearly signaling that they are no longer just catching up—they are attempting to redefine the playing field. The transition from a “Plan B” survival mindset to a “Tau Scaling” innovation model confirms that, despite severe external pressure, the focus has shifted entirely to technical resilience and architectural superiority.
News source: https://peoplesdaily.pdnews.cn/china/er/30052255063?recommd=1&traceId=selfhold&traceInfo=1&sceneId=